Microchip releases suite of Intelligent Advanced Synthesis (HLS) tools

     The combination of performance and low power consumption for edge computing applications is driving the need for developers to use field programmable gate arrays (FPgas) as energy-efficient accelerators, which can also provide flexibility and speed time to market. However, much of the edge computing, computer vision, and industrial control algorithms were developed natively in C++ by developers with little or no knowledge of the underlying FPGA hardware.

     To support this important development community, Microchip Technology introduced an HLS design workflow called SmartHLS as a new addition to its PolarFire FPGA family. SmartHLS can translate C++ algorithms directly into FPGA-optimized register transfer level (RTL) code, greatly improving productivity and ease of design.

     Bruce Weyer, Microchip's vice president of FPGA business unit, said: "SmartHLS enhances the capabilities of Microchip's Libero® SoC design tool suite, enabling the tremendous benefits of the award-winning, medium-bandwidth PolarFire and PolarFire SoC platforms to be leveraged by a diverse group of algorithm developers without having to be FPGA hardware experts. "In combination with Microchip's VectorBlox™ neural network software development Kit, the new suite will greatly improve designer productivity by using C/C++ algorithms and FPGA-based hardware accelerators to develop cutting-edge solutions for applications such as embedded vision, machine learning, motor control and industrial automation."

     Based on the open source Eclipse integrated development environment, SmartHLS Design Suite uses C++ software code to generate HDL IP components for integration into Microchip's Libero SmartDesign project. This enables engineers to describe hardware behavior at a higher level of abstraction than traditional FPGA RTL tools. Compared to other HLS products, it executes hardware instructions concurrently through multithreaded application programming interfaces (apis) and simplifies the expression of complex hardware parallelism, further increasing productivity while reducing development time.

     The SmartHLS tool requires one-tenth as many lines of code as the equivalent RTL design, and the resulting code is easier to read, understand, test, debug, and verify. The tool also simplifies hardware microarchitecture design trade-offs and enables developers to leverage existing C++ software for PolarFire FPGas and FPGA SoCs.