Infineon introduces new OptiMOS source bottom power MOSFETs

     High power density, excellent performance and ease of use are key requirements in current power system designs. To this end, Infineon Technologies AG has launched a new generation of OptiMOS Source-Down (SD) power MOSFETs that provide practical solutions to design challenges in end applications. Housed in a PQFN package, the power MOSFET measures 3.3 x 3.3 mm2 and supports a wide voltage range from 25 V to 100 V. This package enables higher efficiency, higher power density, industry-leading thermal performance, and lower BOM cost, setting a new industry benchmark in power MOSFET performance. The device has a wide range of applications, including motor drives, SMPS for servers, telecom and OR-ing, and battery management systems.

     Compared with the traditional Drain-Down packaging, the latest source bottom packaging technology can make the device form factor close to the bare chip. In addition, this innovative packaging technology reduces losses, further enhancing the overall performance of the device. Using a source bottom package can reduce RDS(on) by 30% compared to the state-of-the-art drain bottom package. The main advantages that this technological innovation can bring to system design include: shrinking the form factor, moving from SuperSO8 5 x 6 mm2 package to PQFN 3.3 x 3.3 mm2 package, which can reduce the footprint by about 65% and make more available space Effective utilization, thereby improving the power density and system efficiency of the end system.

     In addition, in a bottom-mounted source package, heat is transferred to the PCB through thermal pads rather than through internal wire bonds or copper tape designs to improve heat dissipation. This also reduces the junction-to-case thermal resistance (RthJC) by over 20% from 1.8K/W to 1.4K/W, enabling excellent thermal performance. The two models currently launched by Infineon occupy different board areas. They are SD standard gate layout and SD gate center layout. In the standard gate layout, the location of the electrical connections remains the same, allowing a simple and direct replacement of the standard drain bottom package with the new source bottom package; in the center gate layout package, the gate pins Moved to the center position to facilitate parallel connection of multiple MOSFETs. Both models enable optimized PCB layout, resulting in reduced parasitics, improved PCB losses, and ease of use.