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Cypress expands the flexible PSoC 4 product line based on 32-bit ARM Cortex-M0

Mar 8 2015 2015-03 Semiconductors Cypress Semiconductor
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Cypress Semiconductor Corporation announced the launch of a new product family in the PSoC 4 programmable system-on-chip architecture. The new PSoC 4 M Series extends the award-winning PSoC 4 architecture with additional programmable analog and digital modules, 128KB of flash memory, a direct memory access controller, two control local Area Network (CAN) interfaces, and 55 general-purpose I/O and 32-bit ARM®-Cortex®-M0 cores. Making it a natural choice to replace existing 8-bit and 16-bit applications.

     Cypress Semiconductor Corporation announced the launch of a new product family in the PSoC 4 programmable system-on-chip architecture. The new PSoC 4 M Series extends the award-winning PSoC 4 architecture with additional programmable analog and digital modules, 128KB of flash memory, a direct memory access controller, two control local Area Network (CAN) interfaces, and 55 general-purpose I/O and 32-bit ARM®-Cortex®-M0 cores. Making it a natural choice to replace existing 8-bit and 16-bit applications. In addition, these devices bring the design flexibility of the PSoC architecture to a variety of sensor-based systems, such as home appliances, automotive, system management and control applications.

 

     John Weil, vice president of Marketing for Cypress PSoC, said: "Our PSoC 4 product line enables customers to replace their 8 - and 16-bit MCUS based products for as little as 25 cents to seamlessly transition to 32-bit ARM platforms. The new PSoC 4 M series expands the PSoC 4 product line and enables designers to generate more customized interfaces and analog front ends to add more differentiated features and better performance to their products, creating world-class innovative solutions."

 

     The PSoC 4 M series has 16 programmable digital modules, including 8 timer/counter /PWM modules, 4 serial communication modules and 4 universal digital modules. Cypress's programmable digital module consists of two programmable logic devices, a programmable data channel, and status and control registers. The programmable digital module can be used as a coprocessor to relieve the heavy computational load of the ARM Cortex-M0 core, which has traditionally been available only on 8-bit and 16-bit platforms. In addition, these modules can be used to implement new or customized serial communication interfaces on existing programmable hardware, such as support for pulse density modulation microphones and USB Type-C configuration channel protocols. The emergence of these interfaces often requires traditional microcontroller (MCU) vendors to provide new chip platforms.

 

     The PSoC 4 M series features 12 programmable analog modules, including four highly programmable opamps, four current-output digital-to-analog converters (IDacs), two low-power comparators, a 12-bit SAR ADC, and a CapSense capacitive touch sensing module. Programmable analog modules can be used to create custom on-chip analog front ends to support new end features, such as sensors in wearables, without increasing the cost, size and power consumption of the product. Cypress's industry-leading CapSense capacitive touch sensing technology allows engineers to add advanced features such as proximity sensing and water resistance to the user interface to make it more sophisticated.

 

     The scalable PSoC 4 architecture is supported by the easy-to-use PSoC Creator Integrated Development Environment (IDE), which allows software and hardware to be designed simultaneously, and provides free embedded ics (PSoC components) represented by ICONS in the IDE, thus simplifying system design and accelerating the time-to-market process. These two points also allow rapid prototyping of end applications while reducing common PCB and firmware modifications.

 

     The PSoC 4 M series is based on the PSoC 4 architecture and features five low-power modes to minimize system power consumption. It supports a low leakage current retention power mode, where power consumption is as low as 150nA, while maintaining SRAM, programmable logic, and the ability to wake up via interrupt. It also offers the industry's best non-reserved stop mode with power consumption as low as 20nA and GPIO wake-up capability.

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